Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture

A promising new alternative to efficiently solve the Von Neumann bottleneck problem is adopt In-Memory Computing (IMC) architectures. Beyond arithmetic operations, IMC architectures aim at integrating additional logic operators directly in memory array or/and periphery order provide close computing abilities. However, they are subject manufacturing defects same way as conventional memories. In this paper, a comprehensive model of 128 × bitcell based on 28 nm FD-SOI process technology has been considered analyze behavior 8T SRAM bitcells presence resistive (open and short) injected read port. hierarchical analysis allowing thorough study each defect carried identify their impact both modes, locally defective well globally array. Experimental results show that mode offers most effective detectability resistive-short resistive-open defects.